1. Field of the Invention
The present invention relates to a variable length code decoder, and more particularly to an variable length code decoder for a motion picture expert group (hereinafter, "MPEG")
2. Description of the Background Art
In general, a variable length coding is a method frequently employed for a non-loss data compression, wherein a fixed length code data is converted to a variable length code data depending upon a statistical characteristic of data. Here, the statistical characteristic of data denotes a property in which the more frequently does an image data occur, the shorter codeword is assigned, and the less frequently the longer codeword.
Likewise, when codewords are assigned to all the image data, an average length of codewords may be compressed shorter than that of the codewords of the original data. The image data compression technique of MPEG1 or MPEG2 is adapted in a system of high definition (HD) television to realize an image data playback and high definition.
In order to realize such an image data compression technique, there is required a decoder for fast decoding and processing the codeword length of the compressed image data.
As shown in FIG. 1, the conventional variable length code decoder includes: a bit stream buffer 10 for reading data encoded in an external memory control unit (not shown), temporarily storing therein the read data to reconstitute in 16-bit units, and outputting the resultant data; a data feeding unit 20 for aligning 16-bit unit data outputted from the bit stream buffer 10 to form 32-bit units; a barrel shifter 30 for shifting the data received from the data feeding unit 20, removing unnecessary data or previously decoded data, and outputting the data for being decoded in 16-bit units; a register 40 for temporarily storing therein the data outputted from the barrel shifter 30; a header detecting unit 50 for detecting a syntax header code for MPEG1 and MPEG2 from the data outputted from the register 40; a variable length code symbol decoding unit 60 for decoding the data of variable length code outputted from the register 40; a finite state machine 70 for parsing the syntax of MPEG1 and MPEG2 by use of the data outputted from the register 40, decoding the fixed length code, and controlling the entire composition unit; a sizing unit 80 for sizing the data decoded in and outputted from the finite state machine 70; a multiplexer 90 for selecting one meaningful signal from respective output data of header detecting unit 50, symbol decoding unit 60 and sizing unit 80; a feeding control unit 100 for controlling the data feeding unit 20 and the barrel shifter 30 in accordance with the signal outputted from the multiplexer 90; a data output unit 110 for outputting respective sizes of data received via register 40 via barrel shifter 30, data decoded in finite state machine 70, data decoded in symbol decoding unit 60 and data outputted from sizing unit 80, to an external main controller (not shown) or an inverse quantizer (not shown) in accordance with the control of the finite state machine 70.
The operation and effects of the thusly constituted conventional variable length code decoder will now be described.
The bit stream buffer 10 reads the data encoded in external memory control unit (not shown) and stores temporarily therein to output the stored data to data feeding unit 20 which aligns 16-bit units of data outputted from the bit stream buffer 10.
The barrel shifter 30 which receives data outputted from the data feeding unit 20 shifts the data according to the control of the feeding control unit 100 to remove unnecessary data or previously decoded data, thereby outputting the data for being decoded in 16-bit units.
The data outputted from the barrel shifter 30 is temporarily stored in the register 40 and then outputted to header detecting unit 50, symbol decoding unit 60, finite state machine 70 and sizing unit 80.
The finite state machine 70 parses the data outputted from the barrel shifter 30 with respect to the syntax of MPEG1 and MPEG2 and decodes the fixed length code, and accordingly a control signal for controlling symbol decoding unit 60, sizing unit 80 and data output unit 110 is outputted.
When the data outputted from barrel shifter 30 is provided with a syntax of MPEG2, the header detecting unit 50 detects a header code from the data outputted from barrel shifter 30 and then outputs the detected data to multiplexer 90 and finite state machine 70.
The symbol decoding unit 60 decodes the data outputted from the barrel shifter 30 into variable length codes under the control of the finite state machine 70, and the decoded data is outputted to the data output unit 110, and also the size of the data is outputted to the multiplexer 90.
The sizing unit 80 determines the size of the data received from the barrel shifter 30, thereby outputting the resultant data to finite state machine 70, multiplexer 90 and data output unit 110.
Then, the data output unit 110 outputs the data outputted from the register 40 or the symbol decoding unit 60 to the external main controller (not shown) or the inverse quantizer (not shown) in accordance with the control of the finite state control unit 70.
Meanwhile, the multiplexer 90 selects one meaningful size of data from the respective sizes of data outputted from multiplexer 90, header detecting unit 50, symbol decoding unit 60 and sizing unit 80 to output the resultant data to the feeding control unit 100 which controls the feeding unit 20 in accordance with the data size and determines the data amount for the shifting and then the determined value is outputted to the barrel shifter 30.
Then, the barrel shifter 30 shifts the data outputted from the feeding unit 20 in accordance with a signal outputted from the feeding control unit 100, removes the unnecessary data or the previously decoded data, and outputs the data for the decoding in 16-bit units. Likewise, the above-described operation is repeatedly carried out.
Because the conventional variable length code decoder employs a 16-bit data path, there are secured several hardware-oriented advantages. However, in order to process data with more than 16-bit units, that is, to process the data in header detecting unit 50, symbol decoding unit 60 and finite state machine 70, there are consumed clocks two times as many, thereby necessitating a complicated processing device for the control.
For example, a DCT (Discrete Cosine Transform) coefficient is 17 bits when maximized. In that case, a reading by a 16-bit processing device does not allow the knowledge of DCT coefficient. Only after the once reading of the subsequent 16-bit data, it is possible to recognize and decode the data value.
The fixed length code (FLC) employed with regard to MPEG1 and MPEG2 is fixed in size. Here, MPEG1 is 28 bits and MPEG2 is 24 bits. In order for the header detecting unit 50 to determine the MPEG2 header code (23 "0"s and one "1"), there are required 24 bits. However, only 16 bits are precessed at one time, so that there is required a register for storing therein the 16 bits which are previously read.
As a result, in order to process such data, there are required a device for storing the previously read data and a control unit for processing the stored data, thereby disadvantageously demanding two times of clocks as many. Further, a desired output is difficult to obtain.